Similar to [12], a wide deep N-well isolation area of 150-?µm, tied to a
quiet analog supply pin, is used between the digital circuits and the RF transceiver in order
to reduce substrate coupling. In addition, substrate ground rings that are tied to local
grounds surround the individual RF blocks.
The PCI interface requires a large pin count so many RF friendly packages with a
good backside ground could not be used. A 224-pin BGA with separate analog and digital
ground substrate planes was chosen. Many of the noise isolation techniques that are
applicable on-chip can be extended to the package design. Where possible, sensitive signal
nodes are not routed to package pins. For example, the VCO control voltage node can be
kept completely on-chip with an integrated loop filter. Sensitive nodes that must be
connected to the package, such as the sensitive LNA inputs, are routed orthogonal to noisy
digital output pins to reduce magnetic coupling.
25.5 Experimental Results
The SoC, integrated in a 0.18-?µm five-layer metal CMOS process, occupies a total silicon
area of 41 mm2. A die micrograph is shown in Fig. 25.9. The LNA is placed in the top right
corner for maximum separation from the switching digital logic as possible.
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