The programmable gain is controlled by digital logic that implements an
automatic gain control (AGC) algorithm. The RFVGA output is down-converted to an IF
of 800-MHz by the 2/3 fRF LO. A transmitter feedback signal, which is off during normal
operation, is injected at the output of the RFVGA for transmitter calibration. The output of
the RF mixer is then down-converted to baseband with the 1/3 fRF LO. The I/Q phases of
the IF LO are generated from the 2/3fRF LO by a simple divide-by-2 block consisting of
master-slave differential D-flip-flops. The baseband path includes two sets of offset DACs
An 802.11g WLAN SoC 554
to null the receiver DC offset and two gm-C biquads forming a fourth-order Butterworth
filter response with programmable gain of 41dB in 1dB steps. The filter output is digitized
by two 9-bit ADCs. The baseband gain and the DC offset DACs are controlled by the
digital baseband processor, and the offset is calibrated and stored for different baseband
gain settings.
Figure 25.3: Receiver block diagram.
Fig. 25.4 shows the circuit diagram of the receive dual down-conversion mixer, which
comprises two differential stages. The RF signal is down-converted to 800-MHz in the first
stage using an NMOS Gilbert-cell type mixer topology.
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